Highly Secured High Throughput Efficient VLSI Architecture for AES Implementations
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2012, Vol 1, Issue 7
Abstract
The AES algorithm can be implemented in different styles at programming levels. The paper compares the hardware efficiency of different AES implementations with respect to their area, speed and power performance especially in two different styles – one using controller and the other one is iterative method. These designs were described using Verilog HDL, simulated using Modelsim® and prototyped in Altera’s platform FPGA.
Authors and Affiliations
Ramoji Vasamsetti, P Ganesh, Ch Appala Swamy
Keywords
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