Implementation And Analogy Of Fast Adder Using Fpga
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 1
Abstract
Fast adder is a type of an adder used in digital logic to implement speed by reducing the amount of time required to determine the carry bit. this paper deals with high data rate of implementation of adders on the field programmable gate array(FPGA) it is the best hardware design which is implemented on FPGA, different architecture has been implemented and compare on the basis of design in terms of carry propagation delay, area required, power ,slice occupied and numbers of LUT’S.
Authors and Affiliations
Preeti S. Manohare, Rohit C. Iyer
Keywords
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