Implementation and optimisation of FPGA based network security system using VHDL
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 4
Abstract
The combination of traditional microprocessors and Field Programmable Gate Array(FPGAs) is developing as a future platform for intensive computational computing, combining thebest aspects of traditional microprocessor front-end development with the reconfigurability of FPGAsfor computation-intensive problemsThis paper present the IDEA algorithm with regard to FPGA and the very high speed integrated circuit hardware description language. Synthesizing and implementation of the VHDL code carried out on Xilinxproject navigator, ISE suite. In this paper , an efficient hardware design of the IDEA using modulo (2n+1) multiplier as the basic module proposed for faster, smaller and low power IDEA hardware circuit. Experimental measurement result show that the proposed design is faster and smaller and also consume less power than similar hardware implementation making it a viable option for efficient This paper talks of IDEA 64 bit plain text, 128 bit key and 64 bit cipher text.
Authors and Affiliations
Pravinkumartiwari , ,Momd. abdullah , , Rajesh nema
Keywords
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- EP ID EP115283
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