Implementation of 8-bit Sigma-Delta ADC using 45nm Technology
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 6
Abstract
Design for oversampling sigma-delta (ΣΔ) ADCs is conferred here. In this paper a contemporary design for 8-bit ΣΔ oversampling ADC is presented, in which first order oversampling ΣΔ modulator and the decimation filter is second order Cascaded Integrated Comb (CIC) filter which is utilized. Transistor level circuit design and output simulation of the sigma-delta ADC with a power supply of 1V is presented here. This architecture is implemented by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology.
Authors and Affiliations
Yogita Tembhre, Anil Kumar Sahu
Keywords
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- EP ID EP22250
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