Implementation of Adaptive Equalizer using FPGA

Journal Title: International Journal of Scientific Research and Management - Year 2015, Vol 3, Issue 2

Abstract

The quality of transmitted channel is deteriorated by channel imperfections. This results in high bit error rate at the recei ver which in turn makes recovering the original signal difficult. Channel response is dynamic in nature and there fore to decrease bit error rate, adaptive equalizer is generally used at receiver end. The purpose of this paper is to present the FPGA implementation of adaptive equa lizer

Authors and Affiliations

Rupanjali Grover

Keywords

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  • EP ID EP214717
  • DOI -
  • Views 89
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How To Cite

Rupanjali Grover (2015). Implementation of Adaptive Equalizer using FPGA. International Journal of Scientific Research and Management, 3(2), -. https://europub.co.uk/articles/-A-214717