Implementation of An Efficient Gate Level Modified Square-Root Carry Select Adder Using HDL
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2013, Vol 1, Issue 7
Abstract
Contribution of this work is reduce the area and power of the CSLA by a simple gate level modification. Based on this modification CSLA architecture have been developed and compared with the regular SQRT CSLA architecture. Carry Select Adder is one of the best adders used in many data processing processors to perform fast and robust arithmetic functions. It reduces the area and power consumption and became a reputed one. As co pared to the SQRT CSLA it is increased in delay. In this work we have evaluated the performance based delay, area and power with logical effort and through FPGA design by using Xilinx tool for synthesis and simulation for graphical verification by using Modelsim tool. The result analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
Authors and Affiliations
K. SURYA KUMARI| Assistant Professor, ECE, Pragathi Engineering College, (Affiliated to JNTUK, A.P), K. HEMANTH KUMAR| M.Tech Scholar, Pragathi Engineering College, (Affiliated to JNTUK, A.P)
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