Implementation of Buffer for Network on Chip Router
Journal Title: The International Journal of Technological Exploration and Learning - Year 2014, Vol 3, Issue 1
Abstract
Network-on-Chip (NoC) introduces the design methodology of interconnection network into System-on-Chip (SoC). It overcomes the main disadvantages of traditional busbased SoC, for example, large delay, small link bandwidth and poor scalability, etc. It is widely believed that NoC will replace bus-based architecture to become the mainstream of SoC design methodology. In NoC architecture the processing elements (PEs) communicate with each other by exchanging messages over the network and these messages go through buffers in each router. Buffers are one of the major resources used by the routers in virtual channel flow control.
Authors and Affiliations
Minakshi M. Wanjari| Electronics Engineering Department, PCE, Nagpur, India, Dr. R. V. Kshirsagar| Electronics Engineering Department, PCE, Nagpur, India, Dr. Pankaj Agrawal| Electronics and Communication Engg. Dept. RCOEM, Nagpur, India
Keywords
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