Implementation of Different Low Power Multipliers Using Verilog
Journal Title: The International Journal of Technological Exploration and Learning - Year 2014, Vol 3, Issue 3
Abstract
Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. Multiplication represents a fundamental building block in all DSP tasks. The objective of a good multiplier is to provide a physically compact, good speed and low power consumption. To save significant power consumption of a VLSI design it is a good direction to reduce its dynamic power that is the major part of total power consumption. Two methods are common in current implementations: regular arrays and Wallace trees. The gatelevel analyses have suggested that not only are Wallace trees faster than array schemes, they also consume much less power. However these analyses did not take wiring into account, resulting in optimistic timing and power estimates. Continuous advances of microelectronic technologies make better use of energy, encode data more effectively, reduce power consumption, etc. Particularly, many of these technologies address low-power consumption to meet the requirements of various portable applications. In these application systems, a multiplier is a fundamental arithmetic unit and widely used in circuits. I compare results for 8bit-width the working of different multipliers by comparing the power consumption by each of them. The result of my paper helps us to choose a better option between serial and parallel multiplier in fabricating different systems. Multipliers form one of the most important components of many systems. So, by analyzing the working of different multipliers helps to frame a better system with less power consumption and lesser area.
Authors and Affiliations
Koteswara Rao Ponnuru| M. Tech, Assistant Professor SRK Institute of Technology Vijayawada, A.P., India, Shabeena Begum Mohammad| M. Tech, Assistant Professor SRK Institute of Technology Vijayawada, A.P., India
Keywords
Related Articles
- EP ID EP8552
- DOI -
- Views 412
- Downloads 22
9T SRAM Cell with Improved Self-Controllable Voltage Level Circuits
As the feature size of the transistor is scaled down, the threshold voltages of MOSFETs have been reduced thereby leakage power substantially increases. Furthermore, leakage is the only source of energy consumption in...
Leverage and its Impact on Earnings and Share Price
This study investigates the impact of leverage on earnings and share price of listed companies on Colombo Stock Exchange (CSE) in Sri Lanka. The study was identified 20 companies listed on the CSE for the period from...
A Study on Multi Material Gate All Around SOI MOSFET
As the continuous down scaling of MOSFET device is required to increase the speed and packaging density of it, but it reduces the device characteristics in terms of short channel effect and reverse leakage current. At...
A Probabilistic Determination of Fuzzy System with Evaluation
The term “fuzzy logic†is rather ambiguous because it refers to problems and method that belongs to different field of investigation. it is possible to find three meaning for the expression “fuzzy logicâ€. In i...
Multi-Band Rectangular Microstrip Patch Antenna with Defected Ground Structure and a Metallic Strip
Microstrip antennas and arrays are small in size any easy to manufacture. The proposed antenna is operated in the S-band and X-band with three resonant frequencies. The antenna has two resonance in the X-band used in...