Implementation of Different Low Power Multipliers Using Verilog
Journal Title: The International Journal of Technological Exploration and Learning - Year 2014, Vol 3, Issue 3
Abstract
Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. Multiplication represents a fundamental building block in all DSP tasks. The objective of a good multiplier is to provide a physically compact, good speed and low power consumption. To save significant power consumption of a VLSI design it is a good direction to reduce its dynamic power that is the major part of total power consumption. Two methods are common in current implementations: regular arrays and Wallace trees. The gatelevel analyses have suggested that not only are Wallace trees faster than array schemes, they also consume much less power. However these analyses did not take wiring into account, resulting in optimistic timing and power estimates. Continuous advances of microelectronic technologies make better use of energy, encode data more effectively, reduce power consumption, etc. Particularly, many of these technologies address low-power consumption to meet the requirements of various portable applications. In these application systems, a multiplier is a fundamental arithmetic unit and widely used in circuits. I compare results for 8bit-width the working of different multipliers by comparing the power consumption by each of them. The result of my paper helps us to choose a better option between serial and parallel multiplier in fabricating different systems. Multipliers form one of the most important components of many systems. So, by analyzing the working of different multipliers helps to frame a better system with less power consumption and lesser area.
Authors and Affiliations
Koteswara Rao Ponnuru| M. Tech, Assistant Professor SRK Institute of Technology Vijayawada, A.P., India, Shabeena Begum Mohammad| M. Tech, Assistant Professor SRK Institute of Technology Vijayawada, A.P., India
Keywords
Related Articles
- EP ID EP8552
- DOI -
- Views 420
- Downloads 22
Distributed Cut Detection in Wireless Sensor Networks
A wireless sensor network consists of spatially distributed autonomous sensors to physical or environmental conditions, such as temperature, sound, pressure, etc. and to cooperatively pass their data through the netwo...
Underwater Data Acquisition And Marine Boundary Indication System For Fishermen
Security and safety is the major area where many innovations are found to be developing in our life. Every nation wants to protect its border and its people. In order to achieve this, every country is taking serious s...
Design of Floating Point Arithmetic Logic Unit with Universal Gate
A floating point arithmetic and logic unit design using pipelining is proposed. By using pipeline with ALU design, ALU provides a high performance. With pipelining plus parallel processing concept ALU execute multiple...
Integer Wavelet Transform and Predictive Coding Technique for Lossless Medical Image Compression
Lossless image compression has one of its important application in the field of medical images. Enormous amount of data is created by the information present in the medical images either in multidimensional or multire...
Virtual Wireless Sensor Networks using Cloud-computing
A sensor is a converter that measures a physical quantity and converts it into a signal which can be read by an observer or an electronic instrument. In modern world, billions of physical sensors are used for various...