Implementation of Enhanced NOC Router
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 7
Abstract
VLSI innovation has enhanced in incorporating many cores on a single chip, but association between them is critical. NoC has appeared to be solution for this. In this paper, a novel router which is main part of on-chip network that is well suited for dynamically reconfigurable on-chip-systems is proposed. The designed router is capable of runtime detection of errors occurring while forwarding the packets since it uses error directing mechanism and it also includes self-loopback technique which enhances the performance of network by bypassing the packets when it comes to know that there is fault in the next router and it does so by checking the availability of links. It is well reasonable for the substantial movement adaptable systems and it can confine the flawed parts. Our main idea is to avoid communication failures among the nodes and hence increasing the speed of processing and maintain throughput. The source code is written in VHDL. The designed router is synthesized in XILINX ISE 12.2 and simulation is carried out by using ModelSim 10.1.
Authors and Affiliations
Pallavi B V, Dr. Baswaraj Gadgay, Veeresh Pujari, Vivekanand Bonal
Keywords
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