Implementation of High Speed Area Efficient Fixed Width Multiplier
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 10
Abstract
The aim of project is to design a proposed truncated multiplier with less area utilization and low power comparing with previous multipliers. The proposed method finally reduces the number of full adders and half adders during the tree reduction. While using this proposed method experimentally, area can be saved. The output is in the form of LSB and MSB. Finally the LSB part is compressed by using operations such as deletion, reduction, truncation, rounding and final addition. In previous system, to reduce the truncation error by adding error compensation circuits. In this project truncation error is not more than 1 ulp (unit of least position). So there is no need of error compensation circuits, and the final output will be précised.
Authors and Affiliations
G. Rakesh| MTECH(VLSI), Joginapally BR Engineering College,Yenkapally, Moinabad Mandal , R.R. District, Hyderabad, rakhesh.golla@gmail.com, R. Durga Gopal| JBREC Associate Professor, Joginapally BR Engineering College,Yenkapally, Moinabad Mandal , R.R. District, Hyderabad, rdurgagopal@gmail.com, D. N Rao| JBREC Principal, Joginapally BR Engineering College,Yenkapally, Moinabad Mandal , R.R. District, Hyderabad, principal_jbr@yahoo.com
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