Implementation of High Speed Full Adder Using DTMOS
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 6
Abstract
The power dissipation is a major problem in electronic devices. The importance for Power Management Integrated Circuit (PMIC) is emphasized as battery-powered portable electronics such as smart phone are commonly used. DTMOS technique meets the requirement for the low voltage and high-speed circuits. Due to larger current driving capacity and low leakage current, DTMOS is attractive for low power applications. So in this paper full adder design has been implemented using DTMOS technology and calculated its power dissipation and delay and compare this adder with CMOS adder using cadence tool.
Authors and Affiliations
Shubham Bansal, Dr. Neelam R Prakash
Keywords
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