Implementation of High Speed Vedic Multiplier for Digital Signal Processing Using Multiplexer Based Adder
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 6
Abstract
Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very :important in DSPs for convolution, Fourier transforms, etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. Urdhava tiryakbhyam is the general multiplication formula applicable to all cases of multiplication. The coding is done in Verilog and synthesis is done using Xilinx ISE 14.5. The combinational delay obtained after the synthesis is compared with existing multiplier. Further, this Vedic multiplier is used in matrix multiplication. This Vedic multiplier can bring great improvement in the DSP performance.
Authors and Affiliations
Neha Tyagi, Neeraj Kumar Sharma
Keywords
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