Implementation of Lifting-Based Two Dimensional Discrete Wavelet Transform on FPGA Using Pipeline Architecture
Journal Title: INTERNATIONAL JOURNAL OF COMPUTER TRENDS & TECHNOLOGY - Year 2013, Vol 5, Issue 5
Abstract
This paper presents the implementation of the high speed lifting-based two dimensional discrete wavelet transform (2D-DWT) algorithm on Field Programmable Gate Array (FPGA). Pipelining structure in DWT reduces hardware complexity and memory accesses and speeds up the performance. The conversion of raw image into Hex format is done using MATLAB and the Hex image is loaded into the FPGA Kit. The result of the 2D-DWT provides four filtered images and is passed to display. The algorithm has been realized in Verilog HDL and implemented using Xilinx Spartan-6 FPGA device. The lifting procedure to perform the DWT operation is folded architecture where in first stage each row of the raw image is processed to generate the approximate coefficients (L) and Detailed (H) and the output generated is stored back in the corresponding locations. In second stage each of the L and H is transposed and given to 1-D engine, which this time does the DWT operation row wise, but it results in column wise because of previous transpose operation. The DWT engine is run twice on L and H data to generate further subdivided images LL, LH, HL and HH.
Authors and Affiliations
Raghavendra G , Mrs. Anita R
Keywords
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