Implementation of Optimized 64 Bit MAC using Vedic Multiplier and Reverse Logic Gate
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 3
Abstract
In advanced digital signal processing the MAC (multiply and accumulate unit) unit acquires the predominant role. The optimized MAC unit deals with improvising the speed, area power consumption. The high speed processors rely on multiplication operation as they are the core of many DSP applications today. The multiplication is done using the ancient Vedic multiplication and the addition is carried out by reversible logic gate. The Vedic multiplier is used so as to reduce the partial product generation and reduces the latency. Reversible logic is used to reduce the power dissipation and to resist information loss. The carry select adder is used as it is the fastest addition adder and the speed is due to the limited carry propagation from input to output. The optimization of MAC unit design is programmed using Verilog - HDL using Xilinx ISE 14.7 and the FPGA implementation is done on Spartan3E.
Authors and Affiliations
Savitha S, S. Raja, Amrutha Soroobini S, Anusruthi K, Barani Priya L
Keywords
Related Articles
- EP ID EP23692
- DOI http://doi.org/10.22214/ijraset.2017.3230
- Views 297
- Downloads 5
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