Implementation of Parallel MAC Unit in 8*8 PreEncoded NR4SD Multipliers
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2016, Vol 5, Issue 5
Abstract
This paper describes a merged multiplyaccumulate (MAC) hardware along with the pre-encoded non redundant radix-4 signed digit encoding (NR4SD) multiplier. New designs of pre-encoded multipliers are explored by off-line encoding the standard coefficients using NR4SD encoder and storing them in system memory.The NR4SD encoder, CSA tree, the NR4SD multiplier, and the accumulator sections ensure the fastest possible implementation. A fast pipelined 8 * 8 multiplier implementation is proposed in the paper with parallel multiply-accumulate unit. Extensive experimental analysis verifies the gains of the proposed pre-encoded NR4SD multipliers with MAC unit in terms of area complexity and power consumption compared to the conventional MB multiplier.
Authors and Affiliations
Justin K Joy, Deepa N R, Nimmy M Philip
Keywords
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