Implementation of Sub-Threshold Source Coupled Logic for Ultra-Low Power Application
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 4
Abstract
This thesis work generally focuses on the use of sub-threshold source combined logic (STSCL) for building digital circuits and systems working at very low voltage and promise to provide desirable performance with excellent energy savings. Industries like bio-engineering and smart sensors require the energy consumption to be effectively very low for long battery life. Alongside interacting with the ultra-low power requirements, the device must also be reliable, robust, and perform well under harsh conditions. In this thesis work, logic gates are designed and analysed, using STSCL. These gates are further used for implementation of digital subsystems in small-sized smart dust sensors which would operate at very low supply voltages and consume extremely low electricity. The simulated results are studied, analysed and as opposed with same CMOS-based digital circuits. The results show on the good thing about STSCL-based digital systems over CMOS.
Authors and Affiliations
B. V. Ramana, S. Md. Imran Ali, P. Nagashyam, Y. Sandeep
Keywords
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