Implementation of VLSI Based Router for Custom Network On Chip Applications
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 11
Abstract
A fast full-chip synthesis method to construct network-on-chips (Custom Noc) for network on chip based systems.It can be used for irregular network topology for specific designs with already known communication demands. In this method processing elements and the communication architectures are to be synthesized simultaneously in the floor planning process, thus it is called Custom Noc process. CusNoc synthesizes in two steps. The desired network topology is generated first and it depends on already existed communication analysis. In this process, the Processing elements have to be partitioned into groups and a router is assigned to each group so the utility of routers can be maximum. So, the number of routers passed by a packet or hops is minized, thus reduces power consumption. Finally, network topology is formed by properly connecting these groups. Here the router is a ‘Network Router’ that it has a one input port and the packet enters through this port .There are five output ports to where the packet can be driven out.Packet contain two parts and they are data(payload) and address sequence. The width of Packet which carries information is 8 bits and length of packet transferring may be from 1 to 32 bytes.It drives the packet to destination ports corresponds to the address sequence in the packet. Each output port contains 3-bit unique address. The switch drives the packet to the output port,when the destination address in the packet matches with any the output port address, The packet contains 5-bit data.In this paper uses Xilinx ISE tool for synthesizing and Modelsim for simulation.
Authors and Affiliations
G. Jaya Lakshmi, S. Sri Vidya
Keywords
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