Improved Fused Floating Point Add-Subtract Unit
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 9
Abstract
This paper presents improved architectures for a fused floating -point add–subtract unit. The fused floating -point add–subtract unit is useful for digital signal processing (DSP) applications such as fast Fourier transform (FFT) and discrete cosine transform (DCT) butterfly operations. To improve the performance of the fused floating -point add–subtract unit, a dual-path algorithm and pipelining are employed. The fused floating-point add– subtract unit saves the area compared to a discrete floating -point add–subtract unit. The dual-path design reduces the latency compared to the discrete design. Based on a data flow analysis, the proposed fused dualpath floating -point add–subtract unit can be split into two pipeline stages, the throughput is increased compared to the nonpipelined dual-path design.
Authors and Affiliations
Kunapareddy S Nagendra, D. Suresh
Keywords
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