Loss Reduction Using the Smart Power Flow Controller by Tap-Changing Algorithm of Sen Transformer
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 3
Abstract
The transmission systems is to handle the power efficiently from generation stations to load stations. Even though a considerable amount of power is lost in transmission network components. As a result, a appropriate power flow control devices used to increase the transmission efficiency is implemented. However, the inserted power flow control devices itself consume power which may increase the power loss further. In this paper, Sen Transformer (ST) is recommended for power loss reduction which is capable of regulating the active and the reactive power flow by selecting the best combination of tap-settings of the ST. The tap-changing algorithm of the ST has been implemented through a FORTRAN code. Thus the Phase Angle Regulator (PAR) and Sen Transformer (ST) are connected to a five bus test system using MATLAB/SIMULINK. The results obtained from the simulation results of the ST are compared with the results of the UPFC. The comparison shows better results and hence the performance of the ST is preferred.
Authors and Affiliations
Junia. D, Dr. K. Elango
Intelligent Forms Processing System
The reading part of words is one of the most complex tasks in automated forms processing. The project describes an integrated real time system to read names and addresses on forms. The Name and Address Block Reader (NAB...
Image-Based 3D Reconstruction
We present various method for the reconstruction of Image based structures. from the field of computer vision with surface editing techniques, method to reconstruct 3D character models from video, design of an interact...
Evolutionary Technique for Network Routing
Applying mathematics to a problem of the real world mostly means, at first, modeling the problem mathematically, maybe with hard restrictions, idealizations, or simplifications, then solving the mathematical problem, an...
VLSI Hardware Modelling Of Multifunction GF Architecture for Cryptographic Devices
this paper presents a hardware structure for polynomial binary-to-residue number system (PRNS) conversion using parallel field structures. This structure is based only on polynomial multipliers along with GF architectur...
FPGA Implementation of 64-bit fast multiplier using barrel shifter
In this paper we have described the implementation of a 64-bit Vedic multiplier which is enhanced in terms of propagation delay when it is compared with conventional multiplier like modified booth multiplier, Wallace tr...