Low Complexity Reliability Based Message Passing Decoder Architecture For Non Binary LDPC Codes
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 7
Abstract
Non-binary low-density parity-check (NBLDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance complexity tradeoffs than previous algorithms. This paper first proposes enhancement schemes to the iterative hard reliabilitybased majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E)- IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NBLDPC codes. our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
Authors and Affiliations
Maddirala Kranthi Kiran| M.Tech Student (VLSI System Design) Srinivasa Institute of Science And Technology, kadapa Email-Id: mkranthi440@gmail.com, G Venkata Karthik| Assistant Professor Srinivasa Institute of Science and Technology, kadapa
Keywords
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