Low-Error and High-Throughput Discrete Cosine Transform (DCT) Design
Journal Title: International Journal of Science Engineering and Advance Technology - Year 2014, Vol 2, Issue 11
Abstract
In this paper, by operating the shifting and addition in parallel, an error-compensated addertree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and highthroughput discrete cosine transform (DCT) design. Many DCT architectures were proposed on systolic design to reduce the number of multipliers in the systolic design as multipliers consumes high power and occupy less area . Instead of the 12 bits used in previous works, 9-bit distributed arithmeticprecision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. He proposed 2-D DCT core synthesized by usingXilinx ISE 9.1, and the Xilinx XC2VP30 FPGA can achieve 792 megapixels per second (Mpels/sec) throughput rate.
Authors and Affiliations
Mohammad Sadiq Ali| Associate Professor ,Department of ECE, Sri Venkateswara College Of Engineering And Technology, Chittor, K Sumanth| Student Department of ECE, Sri Venkateswara College Of Engineering And Technology, Chittor
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- EP ID EP16393
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