Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

Abstract

CMOS based circuits are more susceptible to the radiation environment as the critical charge (Qcrit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 µA.

Authors and Affiliations

S Satheesh Kumar, S Kumaravel

Keywords

Related Articles

A Block Cipher Involving a Key and a Key Bunch Matrix, Supplemented with Key-Based Permutation and Substitution

In this paper, we have developed a block cipher involving a key and a key bunch matrix. In this cipher, we have made use of key-based permutation and key-based substitution. The cryptanalysis carried out in this investig...

 [url=http://thesai.org/Downloads/Volume2No5/Paper%2015-Application%20of%20Fuzzy%20Logic%20Approach%20to%20Software%20Effort%20Estimation.pdf] Application of Fuzzy Logic Approach to Software Effort Estimation[/url]

  The most significant activity in software project management is Software development effort prediction. The literature shows several algorithmic cost estimation models such as Boehm’s COCOMO, Albrecht's' Func...

ABJAD Arabic-Based Encryption

The researcher introduced an enhanced classical Arabic-based encryption technique that is essentially designed for Arab nations. The new algorithm uses the shared key technique where the Keyword system Modulus is employe...

Synchronous Authentication Key Management Scheme for Inter-eNB Handover over LTE Networks

Handover process execution without active session termination is considered one of the most important attribute in the Long Term Evolution (LTE) networks. Unfortunately, this service always is suffered from the growing o...

Actions for data warehouse success

Problem statement: The Data Warehouse is a database dedicated to the storage of all data used in the decision analysis, it meets the customer requirements, to ensure, in time, that a data warehouse complies with the rule...

Download PDF file
  • EP ID EP611424
  • DOI 10.14569/IJACSA.2019.0100760
  • Views 63
  • Downloads 0

How To Cite

S Satheesh Kumar, S Kumaravel (2019). Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation. International Journal of Advanced Computer Science & Applications, 10(7), 433-443. https://europub.co.uk/articles/-A-611424