Low Power And High Speed Sample And Hold For Adc Applications
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 11
Abstract
This Paper describes the improved design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch and better SFDR. The designed sample and hold operates at 100MS/s for input signal amplitude of 1.2Vpp.The circuits are designed using CSM 0.18µm technology incadence environment and power consumption estimated was 6.5 mwatt from 1.2V power supply
Authors and Affiliations
Prity Yadav, Annu Saini
Keywords
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- EP ID EP392638
- DOI 10.9790/9622-0711013338.
- Views 51
- Downloads 0
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