Low-Power Hardware Design of Binary Arithmetic Encoder in H.264
Journal Title: International Journal of Advanced Computer Science & Applications - Year 2017, Vol 8, Issue 7
Abstract
Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications.
Authors and Affiliations
Ben Hamida Asma, Nedra Jarray, Zitouni Abdelkrim
Keywords
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- EP ID EP260617
- DOI 10.14569/IJACSA.2017.080756
- Views 109
- Downloads 0
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