LOW POWER HIGH PERFORMANCE ANALYSIS FOR 64 BIT ARITHMETICAL LOGICAL UNIT
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 5, Issue 5
Abstract
As we know we are in the age of Internet of things based technology . Where every device is control by the web or app applications so for those type of technology there is need of fast system which will compute the data as fast as possible with less battery consumption. The core of every embedded device and processor which in turn uses ALU as the workhorse. As we know if workhorse require less power, speed and area so based on that workhorse complete system will make justice with SPAA metrics (Speed, Power, Area and Accuracy). This project proposed an architecture of 64 bit General Purpose ALU .The critical power dissipation can be avoided by the application of clock gating of the hardware required and improving architectural approach for this in which we divide ALU is four sub block of 16-16 bit. These 64 bit ALU is identify input bit and according to that it will perform operation. Due to these logic we can save power consumption. The synthesized architecture will be implemented by Hardware descriptive language (Verilog). Analysis will be performing on on FPGA (Field Programmable Gate Array) level.
Authors and Affiliations
Shikha Gupta
Keywords
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- EP ID EP96053
- DOI 10.5281/zenodo.52497
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