Low Power/ High Speed Design in VLSI with the application of Pipelining and Parallel processing
Journal Title: INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY - Year 2012, Vol 2, Issue 3
Abstract
The main objectives of any VLSI design are Power, Delay andArea. Minimizing all the objectives is a challenge in presentsituation but all efforts to achieve one of these can lead to abetter design. This paper proposes an EDA tool for low power/high speed VLSI design, which solves any DFG to estimate thespeed of operation and the percentage reduction in the powerconsumption using pipelining and parallel processing concepts
Authors and Affiliations
Shilpa Sathish, C. Lakshminarayana
Keywords
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- EP ID EP649838
- DOI 10.24297/ijct.v2i3b.2699
- Views 76
- Downloads 0
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