Low Power Nine-bit Sigma-Delta ADC Design Using TSMC 0.18micron Technology
Journal Title: The International Journal of Technological Exploration and Learning - Year 2013, Vol 2, Issue 5
Abstract
In Sigma-Delta analog to digital conversion method, the input signal is represented by a sinusoidal signal of magnitude 1V at a signal band of 1MHz.The modulator is operated with ±1.8V supply voltage and a fixed oversampling ratio of 128. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 32. It achieves a resolution of 9-bits by occupying silicon chip area of 8043µm2 and by consuming a total power of 540.48nW. A first order sigma-delta modulator, which is implemented using TSMC 180nm technology using Mentor Graphics Pyxis tool and the second order CIC decimation filter is implemented in Verilog HDL.
Authors and Affiliations
Subhashree S. Biswal| M. Tech (ETC) CVRCE, Bhubaneswar, India, Swagat Nanda| Assistant Professor (ETC) CVRCE, Bhubaneswar, India, Prithviraj Kabisatpathy| Professor (ETC) CVRCE, Bhubaneswar, India
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