Abstract

Reduction of propagation delay is very important for high speed applications. This paper gives an idea about the delay reduction on divided-by-4/5 counter. The delay is reduced by domino logic. Dynamic domino logic circuits are widely used in advanced digital Very Large Scale Integration (VLSI) circuits because it is uncomplicated to implement and low cost. Domino logic is a CMOS based approximation of the dynamic logic techniques. It was technologically advanced to speed up the circuit. Compare to static Complementary Metal Oxide Semiconductor (CMOS) logic, dynamic domino logic deals better performance. Domino gates naturally consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static Complementary Metal Oxide Semiconductor (CMOS) gate. In this paper, dynamic logic flip-flop such as Extended True-Single-Phase-Clock (E-TSPC) flip-flop based divided-by-N/N+1 counter is used for high speed and low power applications. And the proposed work is then compared with the static Complementary Metal Oxide Semiconductor (CMOS) logic.

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