MINIMISATION OF LEAKAGE (SPILLAGE) CURRENT IN CMOS CIRCUITS USING INPUT VECTOR
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 0, Vol 4, Issue 8
Abstract
In CMOS circuits, the lessening of the edge voltage because of voltage scaling prompts increment in sub limit spillage current and thus, static force scattering. We have proposed a novel strategy called LECTOR for outlining CMOS entryways which fundamentally chops down the spillage current without expanding the dynamic force scattering. In the proposed system, we present two leakage control transistors (a p - sort and a n - sort) inside of the rationale door for which the entryway terminal of every spillage control transistor is controlled by the wellspring of the other
Authors and Affiliations
Jyoti Saini
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- EP ID EP89752
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