Modeling A New Architecture Of Area Delay Efficient 2-D Fir Filter Using VHDL
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 1
Abstract
This paper presented memory footprint and combinational complexity for two - dimensional finite impulse response (FIR) filter to get the systematic design strategy to obtain areadelay-power-efficient architectures. Based on the memory sharing and memory-reuse along with suitable scheduling of computational design of storage architecture the separable and nonseparable filters with less memory footprint are obtained. To overcome this low performance filter a novel block based structures is presented and observe the significance change on it.
Authors and Affiliations
J Geetha, J. E. N. Abhilash, D Sekhar
Keywords
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- EP ID EP28133
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