Modelling of MIB Based SPLDs for Future Computing
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 4
Abstract
Designing low power ultra dense digital circuits are considered both fascinating and challenging technology in post CMOS era. SET (Single Electron Transistor) technology came up as a promising candidate and is largely accredited owing to their higher acceptability in today’s academia and industry. This research endeavour insights the novelty of SETs in the vicinity of fabrication and room temperature operation. But in both the cases SETs is some how lagging behind. In such, a comparatively new concept of hybridising CMOS with SETs reveals new prospect in device research. The Mahapatra-Ionescu-Banerjee (MIB) model based on this hybrid CMOS-SET is pioneer in bridging the gap in CMOS and SETs. The Authors here demonstrate a hypothetical model of hybrid CMOS-SET Simple Programmable Logic Devices (SPLDs).
Authors and Affiliations
Dr. J Gope, Rahul Kumar Sah, Sanjay Bhadra, Mahuya Panda
Keywords
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- EP ID EP20327
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