Abstract

: Residue number system (RNS) is an unconventional non-weighted integer number representation system that uses residues of a number in particular modulus for its representation. Forward converters, modulo arithmetic units, reverse converters are the main part of the residue number system. The reverse converter in the existing residue number system is based on regular and modular adders. It shows significant power consumption and low speed. This is the main reason which prevents the use of Residue Number system in high speed applications. The new reverse converter design method for 4n-moduli set based on the New Chinese remainder theorem. The modified reverse converter design employs the Hybrid-Modular-Parallel prefix-Excess-one modulo (2n-1) adder (HMPE) and Hybrid Regular Parallel prefix Xor/or adder (HRPX). They provide delay and power efficient reverse converter design. The VHDL language is used for coding. Synthesis is done in Xilinx ISE design suite 13.2 and ModelSim SE 6.3f is used for simulation.

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