Modular Design of Adders with Domino Logic 1
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 4
Abstract
- Based on 180nm CMOS technology a 4 bit domino logic adder is designed for speed optimization over ripple carry adder. The adder is designed using 4 bit slice of carry look-ahead adder. Multiple slices are may be connected in ripple carry fashion to obtain higher order adders like 8, 16, 32 and others. This result in considerable reduction in time as compared to nominal ripple carry adder. Equations of sum, generate and propagate are implemented in domino CMOS logic using TSMC 180nm library to provide energy optimization. A 64 bit adder designed using 16 slices of Carry look-ahead adder gives latency of no more than time equivalent to 33 clocks with a transistor count of 1504. Average power results are also presented in this paper with selected input vectors. Average power is 4.65 microwatt
Authors and Affiliations
M. B. Damle, , Dr. S. S. Limaye,
Keywords
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