Multi Core Processor Arrays Cores Optimization in AES Engines

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Multi Core Processor Arrays Cores Optimization in AES Engines

Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 2

Abstract

In the present scenario protecting the sensitive information is done by several encryption standards. AES encryption is modern technique which is based on the principle of substitution-permutation network. Advanced encryption standard is well known as the symmetric key standard for encryption and decryption of blocks of data. In encryption, the AES accepts a plaintext input, which is limited to 128 bits, and a key that can be specified to be 128 bits to generate the Cipher text. Software implementation of AES is now extended to hardware also. Due to this hardware implementation, there is a tremendous improvement in the throughput & energy efficiency. By exploring different granularities of AES as a One round encryption, Nine loop Encryption, Parallel Mixed Column and Full Parallelism and mapping these implementations on a field programmable gate array system. In comparison with published AES cipher implementations on general purpose processors the proposed design has occupied less area and small delay.. AES analysis is performed on all levels of abstraction (verilog). The motivation behind the work is to optimize area, faster processing. AES algorithm is simulated at different levels in CADENCE to ensure that the design optimizes power, area and delay.

Authors and Affiliations

Chandrahas Reddy. M

Keywords

One round encryption Nine loop Encryption Advanced encryption standard (AES) Field Programmable Gate Array (FPGA)

EP ID EP21597
DOI -
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