Multiple Logic Styles for Low Power VLSI
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 10
Abstract
In this review paper, full adder was designed using CMOS logic, pass transistor logic (PTL), transmission gate logic (TG) styles. We are going to compare adiabatic full adder using ECRL & PFAL logics with conventional designs and they are simulated using Tanner software. It is finding that adiabatic technique is good choice for low power applications in specific frequency range. The power dissipation in conventional CMOS circuit can be reduced through energy recovery principle.
Authors and Affiliations
Baljinder Kaur, Narinder Sharma
Keywords
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