Multiplication Algorithms for VLSI - A Review
Journal Title: International Journal on Computer Science and Engineering - Year 2012, Vol 4, Issue 11
Abstract
In today’s digital world, where portable computers have become as small as the size of palm limitation on processing speed has increased. Thus there’s a need for modification in the traditional approach to overcome this limitation. An implementation using parallel and pipelined approach could work at higher speed while occupying limited number of slices. Paper deals with analyzing and reviewing different multiplication algorithms viz. Vedic, Chinese, Wallace, Booth, Karatsuba and Toom-Cook by performing 11*8 bit multiplication using parallel and pipelined approach.
Authors and Affiliations
Piyush S. Kasat , Devendra S. Bilaye , Harish V. Dixit , Rahul Balwaik , Amutha Jeyakumar
Keywords
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