A FPGA Implementation of Memory Efficient Distributed Arithmetic Fir Filter
Journal Title: International Journal of Computer Science Engineering and Technology (IJCSET) - Year 2012, Vol 2, Issue 9
Abstract
Finite impulse response (FIR) filters are the most popular type of filters implemented in software.[/b] An FIR filter is usually implemented by using a series of delays, multipliers, and adders to create the filter's output. To implement fir filter based on DA(distributed arithmetic) algorithm is directly applied in FPGA(field programmable gate array),it is difficult to achieve the best configuration in the coefficients of fir filter, memory and computational speed.[/b] This paper provides the Distributed Arithmetic can save considerable hardware resources through using LUT to take the place of MAC units. Another virtue of this method is that it can avoid system speed decrease with the increase of the input data bit width or the filter coefficient bit width, which can occur in traditional direct method and consume considerable hardware resources. The design based on Altera chips is synthesized under the integrated environment of quartus II 9.0. The results of simulation and test shows that this method reduces the FPGA hardware resources, memory size and high speed is achieved. This design has greatly improves memory efficient though FPGA realization.[/b]
Authors and Affiliations
Bhagyalakshmi. Basuvula , B. N. Srinivasa Rao
Keywords
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