A Genetic Approach for Area Reduction in VLSI Layout
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 4
Abstract
Very-large-scale-integration (VLSI) is defined as a technology that allows the construction and interconnection of large numbers (millions) of transistors on a single integrated circuit. Integrated circuit is a collection of one or more gates fabricated on a single silicon chip. The major objective in designing of VLSI integrated circuits is overall chip area reduction. Genetic Algorithm is an iterative and evolutional approach that could be applied to VLSI module placement problem. In this paper a Genetic Algorithm based approach is proposed to reduce the chip area by means of effective placement of the modules. Major placement constraints are considered such that the modules are placed based on best fit position values. As an idea to improve the result of final floor plan, a condition is given such that the modules whose heights are greater than the width in their dimensions are rotated 90 degrees (i.e.) the height is converted into width and the width into height. This yield an area optimized floor plan.
Authors and Affiliations
J. Allwyn Vinoth*
Keywords
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- EP ID EP163916
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