A Review of FPGA-based design methodologies for efficient hardware Area estimation

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 A Review of FPGA-based design methodologies for efficient hardware Area estimation

Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2013, Vol 13, Issue 4

Abstract

 In recent years, FPGA’s have become increasingly important and have found their way into system design. So, the desire emerges for a means that allows early area and performance estimation Understanding how a design maps to them and consumes various FPGA resources can be difficult to predict, so typically designers are forced to run full synthesis on each iteration of the design. For complex designs that involve many iterations and optimizations, the run-time of synthesis can be quite prohibitive .However, to achieve high performance; FPGA must be supported by efficient design methodology and optimization techniques. The motivation behind this work is to review different FPGA based design methodology and optimization techniques that can be employed to efficiently estimate hardware area utilized in terms of look up table (LUT’S) or configurable logic blocks (CLB’S).

Authors and Affiliations

Rachna Singh

Keywords

EP ID EP146738
DOI -
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