Design & Implementation Of 32-Bit Risc (MIPS) Processor
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 4, Issue 10
Abstract
In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions and addressing modes on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. Our proposed RISC MIPS Processor technique sends the machine code to the instruction memory of the soft-core from the software tool through UART. The user should use that software tool to write MIPS assembly code, debug the code and generate the machine code. Also, the software tool is used for establishing UART connection.
Authors and Affiliations
Marri Mounika , Aleti Shankar
Keywords
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- EP ID EP109786
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