Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Using Reversible Adder
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2013, Vol 3, Issue 5
Abstract
This work is devoted for the design and FPGA implementation of a 16bit Arithmetic module, which uses Vedic Mathematics algorithms. For arithmetic multiplication various Vedic multiplication techniques like Urdhva Tiryakbhyam Nikhilam and Anurupye has been thoroughly analyzed. Also Karatsuba algorithm for multiplication has been discussed. It has been found that Urdhva Tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers. Using Urdhva Tiryakbhyam, a 16x16 bit Multiplier has been designed and using this Multiplier, a Multiply Accumulate (MAC) unit has been designed. Then, an Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Model sim 6.5.Further, the whole design of Arithmetic module has been realized on Xilinx Spartan 3E FPGA kit and the output has been displayed on LCD of the kit. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns. The further extension of this 8 x 8 Array multiplication and Urdhava multiplication can be implemented by using reversible DKG adder replacing with adders(H.A or F.A), and by using 16 x 16 – bit, 32 X 32 – bit are more than that. It can be dumped in to Xilinx tools, and also finding the comparison between the adders like power consumption, speed etc..,
Authors and Affiliations
V S Chunduri, G. Lakshmi, Dr. M. Prasad
Keywords
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