Design and Performance analysis of Low power CMOS Op-Amp
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 2, Issue 9
Abstract
This paper proposes a low power CMOS operational amplifier which operates at 1.8 V power supply. The unique behavior of the MOS transistors in sub-threshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Designing of two-stage Op-Amp is a multi-dimensional optimization problem where optimization of one or more parameters may easily result into degradation of others. The Op-Amp is designed to exhibit a unity gain frequency of 17.3 MHz and exhibits a gain of 62.04dB. The proposed design uses a smaller compensation capacitor (CC), which improves the slew rate and also, benefits for the area of compensation circuit. In order to verify the viability two-stage Op-Amp at SCNO 180 nm CMOS technology is designed and verified and power consumption is reduced.
Authors and Affiliations
Anand Kumar Singh
Keywords
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- EP ID EP148622
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