Design and Simulation of Dct Chip In Vhdl and Application in Watermark Extraction
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2014, Vol 16, Issue 3
Abstract
Abstract: The paper presented the design, modeling and chip implementation of 2D Discrete Cosine Transform (DCT) domain for copyright protection of images, as digital watermarking chip. Recent improvement in computational world and the proliferation of the Internet have facilitated and demanded the production and distribution of unauthorized copies of copyrighted digital contents. The research work involved simulations and synthesis of VHDL code utilizing recent FPGA families of Xilinx, SPARTEN 3E. It is achieving the most demanding real-time requirements of some standardized frame resolutions and rates. The simulation and Synthesis results for 8-point DCT implementations indicate operating frequencies of 50 MHz, and 60 MHz for Xilinx ISE Environment and functional check using Modelsim 10.1 b software.
Authors and Affiliations
Nirabh Agarwal , Arpit Jain , Prof. Sanjeev Sharma
Keywords
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- EP ID EP88643
- DOI 10.9790/0661-16345964
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