Design and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2013, Vol 3, Issue 3
Abstract
Abstract : Today, low power memory is given most priority in VLSI design. The power is most important aspect for today’s technology. So the power reduction for one cell is the vital role in memory design techniques. As the technology growing portable device (e.g. Cell phone, PDA) increases, the Static Power Consumption (Leakage Power) became a significant issue. Leakage current in standby mode is the major part of power loss. We concentrate on the technique that to reduce the leakage current in standby mode. The one CMOS transistor leakage current due to various parameters is the essentiel role of power consumption. The CMOS leakage current to the process level can be decreased by using sleepy keeper technique. The advantages in this technique are ultra-low leakage with dual Vth, state-saving, less area penalty and faster than other techniques like sleepy stack approach, sleep, Zig Zag.This project’s focus is to reduce leakage power consumption of an 6TSRAM by employing Sleepy Keeper technique in different topology
Authors and Affiliations
Bikash Khandal
Keywords
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- EP ID EP87477
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