Design of High Speed Based On Parallel Prefix Adders Using In FPGA
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 2, Issue 12
Abstract
The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power-delay performance of the adder. In VLSI implementations, parallel-prefix adders(also known as carry-tree adders) are known to have the best performance. However,this performance advantage does not translate directly into FPGA implementations due to constraints on logic block configurations and routing overhead. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA). These designs of varied bit-widths were implemented on a Xilinx Virtex 5 FPGA and delay values were taken from static timing analysis of synthesis results obtained from Xilinx ISE design suite 10.1. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 64 bits. The carry- tree adders have a speed advantage over the RCA as bit widths approach 256.
Authors and Affiliations
B Pullarao
Keywords
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