Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells
Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 4, Issue 5
Abstract
The aim of our work is to evaluate the performance of One-bit Hybrid full adder cell. To achieve a good-drivability, noise-robustness, and low energy operations for deep-sub micrometer, we explore Hybrid-CMOS style design. HybridCMOS design styles utilize various CMOS logic style circuit to build new Full Adder with desired performance. This Full Adder is categorized into three modules. We compared the proposed Full Adder cell with conventional static CMOS logic styles Adder Cells like C-CMOS, CPL, TFA, TGA and with some hybrid cells at different Load condition. Each Cell showed different power consumption, Delay, PDP and driving capability. The circuits being studied are optimized for energy efficiency at 0.18um CMOS process Technology
Authors and Affiliations
Sushil B. Bhaisare1 , Sonalee P. Suryawanshi2 , Sagar P. Soitkar
Keywords
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- EP ID EP135795
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