Design of Non-pipelined LC3 RISC Microcontroller

Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2014, Vol 16, Issue 5

Abstract

 Abstract:This paper highlights the designingof data and control path of a non-pipelined LC3 microcontroller with a 16 bit Reduced instruction set. The designing was done using a Hardware Descriptive Language (HDL) System Verilog on the platform Questasim Simulator. We have demonstrated the use of this RISC microcontroller using basic ALU operations- ADD, AND & NOT, and a memory operation- Load Effective Address (LEA).The 16 bit reduced instruction used in the designing has been chosensuch that it’s computing ends in exactly 5 clock cycles.

Authors and Affiliations

Devyani Gera , Mehul Garg

Keywords

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  • EP ID EP100048
  • DOI -
  • Views 96
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How To Cite

Devyani Gera, Mehul Garg (2014).  Design of Non-pipelined LC3 RISC Microcontroller. IOSR Journals (IOSR Journal of Computer Engineering), 16(5), 77-81. https://europub.co.uk/articles/-A-100048