Design Round Robin and Interleaving Arbitration algorithm for NOC
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 3
Abstract
NOCs (Network on Chip) are increasing in popularity because of their advantages: larger bandwidth, and lower power dissipation through shorter wire segments. Communications in large SOCs are so important that many designers have adopted the NOC approach. The challenges consist in offering the best connectivity and throughput with the simplest and cheapest architecture methodology. In this project it is proposed to Design multi-module architecture (Masters or Slaves) for Network On chip configuration. When multi-modules are involved, there is a need to solve the problem of bus contention among the modules, masters and slaves. To resolve this bus contention problem, two algorithms, interleaving and normal Round robin algorithms in this architecture. In the normal mode, the Round Robin design architecture would be implemented and as matter of configurability interleaving mode is also incorporated. Moreover, 6x6 interleaving switch-based crossbar architecture along the proposed mechanism is implemented and verified on Xilinx FPGA Virtex2P XC2VP30. The overall architecture primitive modules are designed, simulated, synthesized and structured in Verilog and by using various FPGA based EDA Tools.
Authors and Affiliations
Boppidi Srikanth
Keywords
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