Efficient Implementation of Low Power 2-D DCT Architecture
Journal Title: International Journal of Modern Engineering Research (IJMER) - Year 2013, Vol 3, Issue 5
Abstract
This Research paper includes designing a area efficient and low error Discrete Cosine Transform. This area efficient and low error DCT is obtained by using shifters and adders in place of multipliers. The main technique used here is CSD (Canonical Sign Digit) technique.CSD technique efficiently reduces redundant bits. Pipelining technique is also introduced here which reduces the processing time.
Authors and Affiliations
Kalyan K, G. V. K. S. Prasad
Keywords
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- EP ID EP141620
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