Empirical Study of 2-bit Fast Adder using Simon 2.0
Journal Title: IOSR Journals (IOSR Journal of Computer Engineering) - Year 2015, Vol 17, Issue 5
Abstract
Abstract : The present context of post CMOS era demands highly sophisticated low power consuming high speed novel integrated chips in nanometer region. SET (Single Electron Transistor) is eventually the highest priority indexed device that are to be incorporated largely in replacing today’s CMOS transistors. Several attempts have been made so far in mobilizing SET in designing future electronic circuits. One such attempt is being reported here in the present work. The target is to model an SET digital 2-bit fast adder to augment the speed of the super computers or large processing systems. Authors, here, have emphasized in deliberately integrating SET logics to design the 2-bit fast adder. A comparative study is annexed to advocate the incorporation of SET in near future.
Authors and Affiliations
Dr. J. Gope (MIEEE), , Tishya Sarma Sarkar, , Sreshtha Ray
Keywords
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